The PE Electrical and Computer: Computer Engineering exam tests your ability to apply computer engineering principles across hardware, software, and systems-level topics in 85 questions within a 9.5-hour appointment. The current official topic list is Data Representation, Computer Architecture, Systems Software, Application Development, Digital Devices, Digital Electronics, Computer Networks and Cybersecurity, and Quality Processes.
These 10 practice problems are independent FE Test Prep examples for solution mechanics, reference lookup, timing, and distractor review. Each one practices a single official topic area, and the topic map below shows which. Ten problems cannot cover an 85-question exam, so treat them as a sample of each area’s style, not the full topic list.
You will need the NCEES PE Electrical and Computer: Computer Engineering Reference Handbook and a calculator to work through these problems. All formulas used are either derived from first principles or found in the reference handbook.
Tip: Try each problem before reading its solution. About 6 minutes a question is the real exam’s average, and the quick lookups should take far less, which buys time for the long derivations.
Problem 1: Two’s-Complement Addition Overflow
An 8-bit ALU adds two signed two’s-complement integers, A = 0110 10112 (+107) and B = 0011 01012 (+53). The 8-bit result register holds 1010 00002. Read as a signed 8-bit value, the result is most nearly:
Show Solution
Answer: A
An 8-bit signed register holds values from −128 to +127, so the true sum may not fit. Read the stored pattern first, then check whether it can be trusted.
Step 1: Read the stored pattern as an unsigned number:
1010 00002 = 128 + 32 = 160
Step 2: Apply the two’s-complement weight of the sign bit:
The most significant bit is 1, so the value is negative: 160 − 28 = 160 − 256 = −96
Step 3: Check for overflow:
The true sum, 107 + 53 = 160, is above +127. Two positive operands produced a negative result, which is the overflow signature. In hardware the overflow flag is the XOR of the carry into the sign bit (1) and the carry out of it (0), so V = 1.
Why the other options are wrong:
- +160 reads the pattern as unsigned, a value an 8-bit signed register cannot hold.
- −128 is 1000 00002, the most negative 8-bit value, not this pattern.
- +127 assumes saturating arithmetic. Ordinary two’s-complement addition wraps around; saturation is a separate mode found in DSP and SIMD instructions.
Key concept: In an n-bit two’s-complement word the sign bit carries a weight of −2n−1, so a pattern with the sign bit set equals its unsigned value minus 2n. Overflow can only happen when both operands have the same sign, and it shows up as a result with the opposite sign.
Problem 2: FIFO Page Replacement
A process references pages in the order 0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4. Physical memory holds 3 page frames, all empty at the start. Using first-in, first-out (FIFO) page replacement, the total number of page faults is most nearly:
Show Solution
Answer: C
FIFO evicts the page that has been resident longest, however recently it was used. Trace the frames one reference at a time, oldest page first:
| Reference | Frames after | Result |
|---|---|---|
| 0 | 0 | Fault |
| 1 | 0, 1 | Fault |
| 2 | 0, 1, 2 | Fault |
| 3 | 1, 2, 3 | Fault, evicts 0 |
| 0 | 2, 3, 0 | Fault, evicts 1 |
| 1 | 3, 0, 1 | Fault, evicts 2 |
| 4 | 0, 1, 4 | Fault, evicts 3 |
| 0 | 0, 1, 4 | Hit |
| 1 | 0, 1, 4 | Hit |
| 2 | 1, 4, 2 | Fault, evicts 0 |
| 3 | 4, 2, 3 | Fault, evicts 1 |
| 4 | 4, 2, 3 | Hit |
Nine of the twelve references fault: 9 page faults.
Where the other options come from:
- 7 is what the optimal (OPT) algorithm achieves on the same string with 3 frames. OPT evicts the page used farthest in the future, which no real system knows in advance.
- 8 undercounts by one, the usual result of tracing in your head instead of on paper.
- 10 is what FIFO produces with 4 frames, and what LRU produces with 3.
Key concept: This reference string is the classic demonstration of Bélády’s anomaly: giving FIFO a fourth frame raises its faults from 9 to 10. Stack algorithms such as LRU and OPT never get worse with more frames; FIFO can.
Problem 3: Setup Timing Slack
A register-to-register path runs on a 10 ns clock. The data path delay, clock-to-Q plus combinational logic, is 6.5 ns. The capturing flip-flop has a 1.2 ns setup time, and clock skew works against this path by 0.3 ns. The setup slack is most nearly:
Show Solution
Answer: B
Setup slack is the time one clock period allows minus the time the data needs to arrive and settle before the capturing edge.
Step 1: Add up the required time:
trequired = tdata + tsetup + tskew = 6.5 + 1.2 + 0.3 = 8.0 ns
Step 2: Subtract it from the clock period:
Slack = Tclk − trequired = 10 − 8.0 = 2.0 ns
Positive slack means the path meets setup timing with 2.0 ns to spare. The same numbers give the fastest clock this path supports: 1 / 8.0 ns = 125 MHz.
Why the other options are wrong: 2.3 ns leaves out the adverse skew. −2.0 ns reverses the sign; negative slack would mean the path fails.
Key concept: A setup check compares the slowest data path against one clock period, so a setup violation can be fixed by slowing the clock. A hold check compares the fastest data path against the same clock edge and does not depend on the period, so a hold violation cannot be fixed that way; it needs more delay in the data path or less skew.
Problem 4: MC/DC Test Coverage
Safety-critical flight software contains the decision if (A && B && C && D), where A, B, C and D are independent Boolean conditions. The minimum number of test cases that achieves modified condition/decision coverage (MC/DC) for this decision is:
Show Solution
Answer: A
MC/DC requires every condition to take both values and to be shown to change the decision’s outcome on its own, with the other conditions held fixed.
Step 1: Pick a base case. With all four conditions true, the AND decision is true: T T T T → true.
Step 2: Flip one condition at a time. Each flip alone makes the decision false, which shows that condition’s independent effect:
- F T T T → false (shows A)
- T F T T → false (shows B)
- T T F T → false (shows C)
- T T T F → false (shows D)
Step 3: Count. The base case pairs with all four flips, so 4 + 1 = 5 test cases. For N conditions the minimum is N + 1.
Why the other options are wrong: 4 leaves out the base case, so no flip has anything to be compared with. 16 is the full truth table (24), exhaustive testing rather than MC/DC. 8 is 2N, the count when every condition gets its own pair of tests with no shared base case; that is enough, but not the minimum.
Key concept: Decision coverage needs only one true and one false outcome, 2 tests here. MC/DC is much stronger, yet it grows linearly with the number of conditions rather than exponentially. DO-178C requires it for Level A airborne software, where a failure could be catastrophic.
Problem 5: Pipeline Data Hazards with Forwarding
A classic 5-stage pipeline (IF, ID, EX, MEM, WB) has full forwarding from the EX/MEM and MEM/WB pipeline registers, and its register file writes in the first half of a clock cycle and reads in the second half. The four instructions below issue back to back. How many stall cycles are needed to resolve the read-after-write hazards on R1?
I1: ADD R1, R2, R3
I2: SUB R4, R1, R5
I3: AND R6, R1, R7
I4: OR R8, R1, R9Show Solution
Answer: D
I1 computes R1 in its EX stage (cycle 3) and writes it to the register file in WB (cycle 5). Check when each dependent instruction needs the value:
- I2 (SUB) needs R1 in EX in cycle 4. I1’s result is in the EX/MEM register by then and is forwarded: 0 stalls.
- I3 (AND) needs R1 in EX in cycle 5. The result has moved to the MEM/WB register and is forwarded from there: 0 stalls.
- I4 (OR) reads R1 in ID in cycle 5, the same cycle I1 writes it back. The register file writes in the first half of the cycle and reads in the second, so I4 gets the new value: 0 stalls.
Every dependent instruction receives R1 in time, so the sequence needs 0 stall cycles.
Where the other options come from:
- 1 stall is the load-use case. If I1 were a load (LW R1), its data would not exist until the end of MEM, one cycle too late for I2’s EX even with forwarding.
- 2 stalls is the result with no forwarding: I2 must wait in ID until cycle 5 to read R1 from the register file.
- 3 stalls assumes no forwarding and a register file that cannot write and read in the same cycle.
Key concept: Forwarding removes every stall between dependent ALU instructions in a 5-stage pipeline. The load-use hazard is the one it cannot remove, which is why compilers try to schedule an independent instruction right after a load.
Problem 6: Finite State Machine: Mealy vs. Moore
A digital designer needs a sequence detector that asserts its output HIGH immediately when the input bit pattern “101” is detected on a serial input line (with possible overlapping sequences). The system uses a single-bit input X and single-bit output Z, clocked by a rising-edge clock. If a Mealy machine is used instead of a Moore machine, what is the minimum number of states required?
Show Solution
Answer: B
A Mealy machine produces outputs that depend on both the current state and the current input, while a Moore machine’s outputs depend only on the current state. This fundamental difference means Mealy machines typically need fewer states.
Step 1: Design the Mealy machine for detecting “101”:
- S0 (initial / no match): Waiting for first “1”
- S1 (seen “1”): Last bit was 1
- S2 (seen “10”): Last two bits were “10”
Transitions: In S2, if input X = 1, output Z = 1 (detected “101”) and return to S1 (since this “1” could start a new overlapping sequence). That gives 3 states.
Step 2: Design the Moore machine for detecting “101”:
Since the Moore output depends only on the state, we need a dedicated output state:
- S0 (initial): Z = 0
- S1 (seen “1”): Z = 0
- S2 (seen “10”): Z = 0
- S3 (seen “101”): Z = 1
From S3 with overlap detection, transitions continue based on the next input. This requires 4 states.
Key concept: A Mealy machine can often detect a sequence with one fewer state than a Moore machine because the output can react to the triggering input in the same clock cycle, without needing a separate “output asserted” state. However, Mealy outputs can glitch between clock edges if the input changes asynchronously, while Moore outputs are synchronized to the clock. On the PE Computer Engineering exam, know how to draw state diagrams for both types and convert between them.
Problem 7: Subnet Mask Calculation
A network engineer must divide the 192.168.10.0/24 network into subnets, each supporting at least 30 hosts. What is the correct subnet mask, and how many usable subnets can be created?
Show Solution
Answer: B
Subnetting requires balancing the number of host bits (for addressable devices) against subnet bits (for the number of subnets).
Step 1: Determine the minimum host bits needed:
Usable hosts per subnet = 2n − 2 (subtracting the network and broadcast addresses).
We need at least 30 hosts: 2n − 2 ≥ 30
24 − 2 = 14 (not enough). 25 − 2 = 30 (exactly 30). So we need 5 host bits.
Step 2: Calculate the subnet mask:
Total address bits: 32. Host bits: 5. Network + subnet bits: 32 − 5 = 27.
Subnet mask = /27 = 255.255.255.224
(The last octet: 256 − 25 = 256 − 32 = 224)
Step 3: Count the usable subnets:
Original network: /24. New mask: /27. Borrowed bits: 27 − 24 = 3.
Number of subnets = 23 = 8 subnets
Step 4: Verify:
Each subnet has 25 = 32 addresses, of which 30 are usable. Total addresses: 8 × 32 = 256 = 28, which correctly accounts for the entire /24 block.
Key concept: When the problem says “at least 30 hosts,” you must find the smallest power of 2 that satisfies 2n − 2 ≥ 30. Using n = 5 gives exactly 30, which meets the requirement. Choosing n = 4 (yielding only 14 hosts) would be insufficient. On the PE Computer Engineering exam, subnetting is a core networking skill, so practice converting between CIDR notation, dotted-decimal masks, and host/subnet counts until it becomes automatic.
Problem 8: Cache Hit Rate Calculation
A processor has a direct-mapped cache with 256 cache lines and a block size of 64 bytes. A program sequentially accesses every element of an integer array containing 4,096 elements (each element is 4 bytes). Assuming the cache is initially empty (cold start), what is most nearly the cache hit rate during the first complete pass through the array?
Show Solution
Answer: C
A direct-mapped cache with spatial locality benefits from loading entire blocks on each miss, so subsequent accesses to the same block are hits.
Step 1: Determine elements per cache block:
Block size = 64 bytes. Element size = 4 bytes.
Elements per block = 64 / 4 = 16 elements
Step 2: Count the total number of blocks accessed:
Total elements = 4,096. Elements per block = 16.
Blocks accessed = 4,096 / 16 = 256 blocks
Step 3: Determine hits and misses per block:
For each block, the first access is a compulsory miss (cold start). The remaining 15 accesses are hits (the block is now in cache).
Since we have 256 cache lines and access exactly 256 distinct blocks sequentially, there are no conflict misses (each block maps to a unique cache line in sequential access of a contiguous array).
Step 4: Compute the hit rate:
Total accesses = 4,096
Total misses = 256 (one per block)
Total hits = 4,096 − 256 = 3,840
Hit rate = 3,840 / 4,096 = 15/16 = 93.75%
Verification: The miss rate = 1/16 = 6.25%. This makes intuitive sense: out of every 16 consecutive accesses within one block, only the first one misses. 100% − 6.25% = 93.75%.
Key concept: The hit rate for sequential access depends primarily on the block size relative to element size. With a block size of B bytes and element size of E bytes, the cold-start hit rate for sequential access is (B/E − 1) / (B/E) = 1 − E/B. Here: 1 − 4/64 = 1 − 1/16 = 93.75%. On the PE Computer Engineering exam, also consider conflict misses (when multiple addresses map to the same cache line) and capacity misses (when the working set exceeds total cache size).
Problem 9: Algorithm Time Complexity Analysis
Consider the following algorithm fragment where n is a positive integer:
count = 0
for i = 1 to n:
for j = 1 to i:
count = count + 1
What is the time complexity of this algorithm, and what is the exact value of count after execution?
Show Solution
Answer: C
Nested loops with a dependent inner bound produce a triangular iteration pattern.
Step 1: Count the total iterations:
The inner loop runs j = 1 to i for each value of i. The total number of iterations of the innermost operation is:
Total = ∑i=1n i = 1 + 2 + 3 + … + n = n(n + 1) / 2
Step 2: Verify with a small example (n = 4):
i=1: j runs 1 time. i=2: j runs 2 times. i=3: j runs 3 times. i=4: j runs 4 times.
Total = 1 + 2 + 3 + 4 = 10 = 4(5)/2 = 10. Confirmed.
Step 3: Determine the asymptotic complexity:
n(n + 1) / 2 = (n2 + n) / 2 = (1/2)n2 + (1/2)n
The dominant term is n2, so the time complexity is O(n2).
Key concept: When the inner loop bound depends on the outer loop variable, you must sum the series rather than simply multiplying the bounds. The sum 1 + 2 + … + n = n(n+1)/2 is one of the most important identities in algorithm analysis. Note that answer D gives n2 for the exact count, which would be the case if the inner loop ran from 1 to n (independent bounds). The dependent bound produces a triangular number, which is roughly half of n2. On the PE Computer Engineering exam, be prepared to distinguish between O(n2) and Θ(n2); both apply here since the sum is exactly quadratic.
Problem 10: RSA Private Key Computation
In a simplified RSA key generation exercise, the following parameters are chosen: primes p = 11 and q = 13, giving n = 143. The Euler’s totient is φ(n) = (p − 1)(q − 1) = 120. The public exponent is chosen as e = 7. What is the private key exponent d?
Show Solution
Answer: C
The RSA private exponent d is the modular multiplicative inverse of e modulo φ(n). That is, we need d such that e × d ≡ 1 (mod φ(n)).
Step 1: Verify that e and φ(n) are coprime:
gcd(7, 120): 120 = 17 × 7 + 1, so gcd(7, 120) = 1. Valid choice of e.
Step 2: Solve 7d ≡ 1 (mod 120):
We need 7d = 1 + 120k for some integer k.
Testing systematically: d = (1 + 120k) / 7
- k = 1: (1 + 120) / 7 = 121 / 7 = 17.29 (not integer)
- k = 2: (1 + 240) / 7 = 241 / 7 = 34.43 (not integer)
- k = 3: (1 + 360) / 7 = 361 / 7 = 51.57 (not integer)
- k = 4: (1 + 480) / 7 = 481 / 7 = 68.71 (not integer)
- k = 5: (1 + 600) / 7 = 601 / 7 = 85.86 (not integer)
- k = 6: (1 + 720) / 7 = 721 / 7 = 103 (integer!)
So d = 103.
Step 3: Verify:
7 × 103 = 721. And 721 / 120 = 6 remainder 1. So 721 mod 120 = 1. Confirmed: 7 × 103 ≡ 1 (mod 120).
Verification of the other options:
- d = 23: 7 × 23 = 161. 161 mod 120 = 41 ≠ 1
- d = 71: 7 × 71 = 497. 497 mod 120 = 17 ≠ 1
- d = 113: 7 × 113 = 791. 791 mod 120 = 791 − 6(120) = 791 − 720 = 71 ≠ 1
Key concept: RSA security depends on the difficulty of factoring n into p and q. If an attacker can factor n, they can compute φ(n) and then easily find d using the extended Euclidean algorithm. For real RSA systems, p and q are each 1,024+ bits, making factoring computationally infeasible. On the PE Computer Engineering exam, you should be able to compute modular inverses for small numbers and understand why the relationship e × d ≡ 1 (mod φ(n)) guarantees that encryption followed by decryption recovers the original message: Med ≡ M (mod n) by Euler’s theorem.
Frequently Asked Questions
What topics appear on the PE Computer Engineering exam?
The current PE Electrical and Computer: Computer Engineering exam covers 8 official topic areas: Data Representation, Computer Architecture, Systems Software, Application Development, Digital Devices, Digital Electronics, Computer Networks and Cybersecurity, and Quality Processes. It has 85 questions in a 9.5-hour appointment.
How should I prepare for the PE Computer Engineering exam?
Plan on about 450–600 problems from our bank across the 8 official topic areas, about a quarter of them spaced re-attempts of earlier misses; PE passers report about 500–900 problems at typical vendor length, and ours are shorter, about 9 minutes each including review. Focus on high-weight architecture, networks/cybersecurity, systems software, digital logic, application development, and quality-process topics. Practice with the NCEES PE Electrical and Computer: Computer Engineering Reference Handbook until you can navigate it quickly under timed conditions.
What Topics Does the PE Computer Engineering Exam Cover?
The current NCEES PE Computer Engineering exam uses 8 official topic areas. Here they are with their official question ranges, largest first, and the problems above that practice each one:
- Computer Architecture (12–18 questions): Problems 5 and 8 (pipeline hazards and forwarding, cache hit rate)
- Computer Networks and Cybersecurity (11–17 questions): Problems 7 and 10 (subnetting, RSA key computation)
- Systems Software (9–14 questions): Problem 2 (FIFO page replacement)
- Application Development (8–12 questions): Problem 9 (algorithm time complexity)
- Digital Devices (8–12 questions): Problem 6 (Mealy and Moore state machines)
- Digital Electronics (8–12 questions): Problem 3 (setup timing slack)
- Data Representation (7–11 questions): Problem 1 (two’s-complement overflow)
- Quality Processes (7–11 questions): Problem 4 (MC/DC test coverage)
How Should You Use These Practice Problems?
Reading solutions is not enough. Active practice builds exam-day fluency. Here are strategies to maximize your preparation:
- Simulate exam conditions. Work all 10 problems in one sitting with only the PE Computer Engineering Reference Handbook open. Give yourself 60 minutes total.
- Diagnose your weaknesses. If networking tripped you up, practice subnetting until you can do it in under a minute. If architecture, digital logic, algorithms, or quality-process wording felt shaky, use the full 8-topic bank to drill those lanes directly.
- Redo problems you got wrong. Wait 48 hours, then attempt the missed problems again without looking at the solutions. Repetition builds the automaticity you need under time pressure.
- Bridge theory to practice. The PE Computer Engineering exam emphasizes applied knowledge. For each formula you memorize, also understand when and why it applies in a real engineering scenario.
Want More Practice?
FE Test Prep includes hundreds of PE Computer Engineering problems with detailed walkthroughs covering the 8 official topic areas on the NCEES PE Computer Engineering exam specification. Every problem is written to support the current exam blueprint.
Our question bank covers the current PE Computer Engineering workflow: representation, architecture, systems software, application development, digital devices, digital electronics, networks/cybersecurity, and quality processes. Start practicing today and build the confidence you need for exam day.